ESMT
M52D32162A
FUNCTIONAL BLOCK DIAGRAM
LWE
Bank Select
Data Input Register
LDQM
1M x 16
1M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS LCBR
LWE
LDQM
LCAS
Timing Register
RAS CAS
CKE
CLK
L(U)DQM
WE
CS
PIN FUNCTION DESCRIPTION
Pin
Name
System Clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
A0 ~ A11
BA
Address
Bank Select Address
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
Row Address Strobe
RAS
CAS
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
Write Enable
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
L(U)DQM
Data Input / Output Mask
DQ0 ~ 15
VDD/VSS
Data Input / Output
Power Supply / Ground
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
VDDQ/VSSQ
NC/RFU
Data Output Power / Ground
No Connection /
Reserved for Future Use
This pin is recommended to be left No Connection on the device.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2009
Revision : 1.6
2/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
