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M52D128168A-7TG 参数 Datasheet PDF下载

M52D128168A-7TG图片预览
型号: M52D128168A-7TG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4手机银行同步DRAM [2M x 16 Bit x 4 Banks Mobile Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器手机
文件页数/大小: 48 页 / 1178 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M52D128168A  
SIMPLIFIED TRUTH TABLE  
A11,  
A9~A0  
BA0  
BA1  
COMMAND  
CKEn-1 CKEn  
DQM  
X
CS RAS CAS WE  
Note  
1,2  
A10/AP  
Mode Register set  
H
H
X
L
L
L
L
OP CODE  
X
Register  
Refresh  
Extended Mode Register  
set  
3
3
3
3
Auto Refresh  
H
L
L
L
L
H
X
Entry  
Self  
Refresh  
Exit  
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
L
H
H
H
X
X
X
Bank Active & Row Addr.  
V
V
Row Address  
L
H
L
Column  
Address  
(A0~A8)  
4
4,5  
4
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
Read &  
L
H
L
H
X
Column Address  
Column  
Address  
(A0~A8)  
Write &  
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
Column Address  
4,5  
6
H
X
Burst Stop  
Bank Selection  
All Banks  
V
X
L
Precharge  
X
H
H
L
X
V
X
X
V
X
X
V
X
Entry  
H
L
X
Clock Suspend or  
Active Power Down  
X
X
Exit  
L
H
L
X
X
X
H
L
X
H
X
V
X
X
H
X
H
X
V
X
H
X
V
Entry  
H
Precharge Power Down Mode  
H
L
Exit  
L
H
H
H
X
X
V
X
DQM  
X
X
7
H
L
L
X
H
H
X
H
L
No Operating Command  
Entry  
Exit  
H
L
L
H
X
X
X
X
Deep Power Down Mode  
H
X
X
X
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)  
Note:  
1.OP Code: Operating Code  
A0~A11 & BA0~BA1: Program keys. (@ MRS). BA1=0 for MRS and BA1=1 for EMRS  
2.MRS/EMRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS/EMRS.  
3.Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge of command is meant by “Auto”.  
Auto/self refresh can be issued only at all banks idle state.  
4.BA0~BA1: Bank select addresses.  
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.  
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.  
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected  
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.  
5.During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6.Burst stop command is valid at every burst length.  
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but  
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Aug. 2009  
Revision: 1.3 7/48  
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