ESMT
M52D128168A
EXTENDED MODE REGISTER SET (EMRS)
The extended mode register stores for selecting PASR; DS. The extended mode register set must be done before any active
command after the power up sequence. The extended mode register is written by asserting low on CS ,RAS , CAS , WE and
high on BA1,low on BA0(The SDRAM should be in all bank precharge with CKE already high prior to writing into the extended
more register). The state of address pins
A0~An in the same cycle as CS ,RAS , CAS , WE going low is written in the extended mode register. Refer to the table for
specific codes.
The extended mode register can be changed by using the same command and clock cycle requirements during operations as
long as all banks are in the idle state. The default value extended mode register is defined as half driving strength and all banks
refreshed.
BA1BA0 A11 A10 A9 A8 A7
A6
DS
A5 A4
0
A3
0
A2 A1 A0 Address bus
PASR Extended Mode Register Set
1
0
0
0
0
0
0
A2-A0
000
Self Refresh Coverage
4Bank
2 Bank (BankA& BankB) or
001
010
(BA1=0)
1 Bank (BankA) or
(BA0=BA1=0)
PASR
011
100
101
111
R
R
R
R
A6-A5
00
01
10
11
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
R
DS
Remark R: Reserved
Internal Temperature Compensated Self Refresh (TCSR)
Note:
1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the three temperature range: 15°C, 45°C and 70°C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
3. It has +/-5°C tolerance
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3 9/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
