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M52D128168A-7TG 参数 Datasheet PDF下载

M52D128168A-7TG图片预览
型号: M52D128168A-7TG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4手机银行同步DRAM [2M x 16 Bit x 4 Banks Mobile Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器手机
文件页数/大小: 48 页 / 1178 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
CAS Latency =3
CAS Latency =2
CAS Latency =3
CLK to valid
output delay
CAS Latency =2
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in CAS Latency =3
Hi-Z
CAS Latency =2
CLK cycle time
Symbol
t
CC
t
SAC
t
OH
t
CH
t
CL
t
SS
t
SH
t
SLZ
t
SHZ
2.5
2.5
2.5
2
1
1
6.5
8
-7
Min
7
9
Max
1000
6.5
8
2.5
2.5
2.5
2
1
1
7
8
Min
7.5
9
-7.5
Max
1000
7
8
M52D128168A
-10
Min
10
12
Max
1000
9
10
2.5
3
3
2
1.5
1
9
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
2
3
3
3
3
2
*All AC parameters are measured from half to half.
Note:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to
the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
6/48