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M52D128168A-7TG 参数 Datasheet PDF下载

M52D128168A-7TG图片预览
型号: M52D128168A-7TG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4手机银行同步DRAM [2M x 16 Bit x 4 Banks Mobile Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器手机
文件页数/大小: 48 页 / 1178 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M52D128168A  
FUNCTIONAL BLOCK DIAGRAM  
CLK  
CKE  
Clock  
Generator  
Bank D  
Bank C  
Bank B  
Row  
Address  
Address  
Buffer  
&
Mode  
Bank A  
Register  
Refresh  
Counter  
Sense Amplifier  
Column Decoder  
L(U)DQM  
Column  
Address  
Buffer  
&
Refresh  
Counter  
CS  
RAS  
CAS  
WE  
DQ  
Data Control Circuit  
PIN FUNCTION DESCRIPTION  
PIN  
NAME  
System Clock  
INPUT FUNCTION  
CLK  
CS  
Active on the positive going edge to sample all inputs  
Disables or enables device operation by masking or enabling all  
inputs except CLK , CKE and L(U)DQM  
Chip Select  
Masks system clock to freeze operation from the next clock cycle.  
CKE should be enabled at least one cycle prior new command.  
Disable input buffers for power down in standby.  
CKE  
Clock Enable  
Address  
Row / column address are multiplexed on the same pins.  
Row address : RA0~RA11, column address : CA0~CA8  
A0 ~ A11  
Selects bank to be activated during row address latch time.  
Selects bank for read / write during column address latch time.  
BA0 , BA1  
Bank Select Address  
Latches row addresses on the positive going edge of the CLK with  
RAS low.  
Row Address Strobe  
RAS  
CAS  
Enables row access & precharge.  
Latches column address on the positive going edge of the CLK with  
Column Address Strobe  
CAS low.  
Enables column access.  
Enables write operation and row precharge.  
Write Enable  
WE  
Latches data in starting from CAS , WE active.  
Makes data output Hi-Z, tSHZ after the clock and masks the output.  
Blocks data input when L(U)DQM active.  
L(U)DQM  
Data Input / Output Mask  
DQ0 ~ DQ15  
VDD / VSS  
Data Input / Output  
Data inputs / outputs are multiplexed on the same pins.  
Power and ground for the input buffers and the core logic.  
Power Supply / Ground  
Isolated power supply and ground for the output buffers to provide  
improved noise immunity.  
VDDQ / VSSQ Data Output Power / Ground  
NC No Connection  
This pin is recommended to be left No Connection on the device.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Aug. 2009  
Revision: 1.3 2/48  
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