ESMT
M52D128168A
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
BA
ADDR
ACTION
Note
CS RAS CAS
WE
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
NOP
NOP
ILLEGAL
2
2
IDLE
CA, A10/AP ILLEGAL
RA
A10/AP
Row (&Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
4
5
5
X
L
OP code
X
OP code
X
H
H
L
X
X
X
X
X
2
2
Row
Active
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
CA, A10/AP Begin Read ; latch CA ; determine AP
CA, A10/AP Begin Write ; latch CA ; determine AP
RA
A10/AP
L
H
H
L
X
H
H
L
ILLEGAL
Precharge
ILLEGAL
L
L
X
X
X
X
X
H
H
H
H
L
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
Read
Write
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
L
3
2
H
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
X
X
X
X
X
H
H
H
H
L
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
3
3
2
3
L
H
H
L
X
H
H
L
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
ILLEGAL
X
X
X
X
X
H
H
H
L
Read with
Auto
Precharge
CA, A10/AP ILLEGAL
RA, RA10
ILLEGAL
ILLEGAL
2
2
L
X
X
X
X
X
H
H
H
L
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
ILLEGAL
Write with
Auto
Precharge
X
X
X
X
BA
BA
X
CA, A10/AP ILLEGAL
RA, RA10
X
H
L
ILLEGAL
ILLEGAL
L
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
26/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
