ESMT
M52D128168A
12. About Burst Type Control
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Sequential Counting
Basic
MODE
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Interleave Counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
Random
MODE
Random Column Access
tCCD = 1 CLK
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
At MRS A210 = “000”
At auto precharge. tRAS should not be violated.
1
At MRS A210 = “001”
At auto precharge. tRAS should not be violated.
2
Basic
MODE
4
At MRS A210 = “010”
At MRS A210 = “011”
8
At MRS A210 = “111”
At the end of the burst length, burst is warp-around.
Full Page
tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
Random
MODE
Burst Stop
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
tRDL = 2clk with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
RAS Interrupt
(Interrupted by
Precharge)
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
CAS Interrupt
During read/write burst with auto precharge, CAS interrupt can not be issued.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3 25/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
