ESMT
M52D128168A
6. Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
CLK
C M D
D Q
CLK
C M D
PR E CL= 2
PR E
W R
D0
R D
* N o t e 2
Q3
DQ ( C L 2 )
C M D
Q0
Q1
Q0
Q2
PR E
Q1
D3
D1
D2
tR D L
* N o t e 1
CL = 3
* N o t e 2
Q3
DQ ( C L 3 )
Q2
.
7. Auto Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
CLK
CLK
C M D
C M D
D Q
W R
R D
DQ ( C L 2 )
DQ ( C L 3 )
D0
D2
D1
D3
D2
D0
D2
D3
D1
D1
D0
tR D L ( m i n )
D3
* N o t e 3
Auto Pr ech arge st ar t s
* N o t e 3
Auto Pr ech arge st art s
*Note: 1. tRDL: Last data in to row precharge delay.
2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3 22/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
