ESMT
M52D128168A
10. Clock Suspend Exit & Power Down Exit
1 ) C l o c k S u s p e n d ( = Ac t i v e P o w e r D o w n ) E x i t
2 ) P o w e r D o w n ( = P r e c h a r g e P o w e r D o w n )
CLK
CK E
CLK
CK E
tS S
tS S
Inter nal
Internal
CLK
* N o t e 1
* N o t e 2
CLK
C M D
R D
C M D
NO P
A C T
11. Auto Refresh & Self Refresh
* N o t e 3
1 ) A u t o Re f r e s h
&
S e lf R e f r e s h
C L K
* N o t e 4
* No t e 5
CMD
PR E
CMD
AR
C KE
t RP
t RF C
* N o t e 6
2 ) S e l f Re f r e s h
C L K
* N o t e 4
CM D
SR
PR E
C MD
C KE
t R P
tR F C
*Note: 1. Active power down: one or more banks active state.
2. Precharge power down: all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3 24/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
