ESMT
M52D128168A
3. CAS Interrupt (I)
* No t e 1
1 ) Re a d i n t e rr u p t e d b y R e a d ( B L = 4 )
C L K
C M D
R D
A
RD
B
AD D
D Q( CL 2 )
DQ (C L 3 )
QB1 QB2 QB3
Q A0 QB0
QA0 Q B0 QB1
QB2 QB3
tC C D
* N o t e
2
2 ) W r i t e i n t e r r u p t e d b y W r it e ( B L = 2 )
3 ) W r it e i n t e r r u p t e d b y R e a d ( B L = 2 )
CL K
C MD
WR
WR
RD
W R
t CC D * No t e
2
tC CD * N o t e
2
A
AD D
D Q
B
A
B
D Q( CL 2 )
D A0
D A0
DA 0 D B0 DB 1
t CD L
DB 0 D B1
DQ (C L 3 )
* N o t e
3
D B0 D B1
t CD L
* N o t e
3
*Note: 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access; read and write.
2. tCCD: CAS to CAS delay. (=1CLK)
3. tCDL: Last data in to new column address delay. (=1CLK)
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3 19/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
