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M52D128168A-7TG 参数 Datasheet PDF下载

M52D128168A-7TG图片预览
型号: M52D128168A-7TG
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×16位×4手机银行同步DRAM [2M x 16 Bit x 4 Banks Mobile Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器手机
文件页数/大小: 48 页 / 1178 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M52D128168A  
Precharge command  
( CS ,RAS , WE = Low, CAS = High )  
This command begins precharge operation of the bank selected by BA1 and BA0  
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0. When  
A10 is Low, only the bank selected by BA1 and BA0 is precharged.  
After this command, the DRAM can’t accept the activate command to the  
precharging bank during tRP (precharge to activate command period).  
This command corresponds to a conventional DRAM’s RAS rising.  
Write command  
( CS , CAS , WE = Low, RAS = High)  
If the mode register is in the burst write mode, this command sets the burst start  
address given by the column address to begin the burst write operation. The first write  
data in burst can be input with this command with subsequent data on following  
clocks.  
Read command  
( CS , CAS = Low, RAS , WE = High)  
Read data is available after CAS latency requirements have been met.  
This command sets the burst start address given by the column address.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Aug. 2009  
Revision: 1.3  
15/48  
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