ESMT
M52D128168A
COMMANDS
Mode register set command
(CS ,RAS ,CAS , WE , BA1, BA0 = Low)
The DRAM has a mode register that defines how the device operates. In this
command, A0 through BA0 are the data input pins. After power on, the mode register
set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state. During 2CLK
(tMRD) following this command, the DRAM cannot accept any other commands.
Extended Mode register set command
( CS ,RAS , CAS , WE , BA0 = Low ; BA1= High)
The DRAM has an extended mode register that defines how to set PASR, DS.
Activate command
( CS ,RAS = Low, CAS , WE = High)
The DRAM has four banks, each with 4,096 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A11.
This command corresponds to a conventional DRAM’s RAS falling.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
14/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
