ESMT
M52D128168A
CBR (auto) refresh command
( CS ,RAS , CAS = Low, WE , CKE = High)
This command is a request to begin the CBR refresh operation. The refresh address
is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a row
activate command.
During tRFC period (from refresh command to refresh or activate command), the DRAM
cannot accept any other command.
Self refresh entry command
( CS ,RAS , CAS , CKE = Low , WE = High)
After the command execution, self refresh operation continues while CKE remains low.
When CKE goes to high, the DRAM exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
( CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
16/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
