M32L1632512A
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
BA
(A10)
X
X
X
BA
BA
BA
X
BA
X
DSF
ADDR
ACTION
Note
CS RAS CAS WE
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
L
L
L
L
L
X
H
H
L
H
H
H
H
L
L
L
L
X
H
H
L
L
L
L
H
H
H
L
L
L
X
H
H
H
L
L
L
L
H
H
H
L
X
H
H
H
L
L
L
L
X
H
L
X
H
H
L
L
H
H
L
L
X
H
L
H
H
L
L
H
L
L
H
L
L
X
H
L
L
H
H
L
L
H
L
L
X
X
H
L
L
H
H
L
L
X
X
X
X
L
H
L
H
L
X
X
X
CA
RA
RA
PA
X
NOP
NOP
ILLEGAL
ILLEGAL
2
2
Row Active ; Latch Row Address ; Non-IO Mask
Row Active ; Latch Row Address ; IO Mask
Auto Refresh or Self Refresh
NOP
Auto Refresh or Self Refresh
ILLEGAL
Mode Register Access
Special Mode Register Access
NOP
IDLE
4
5
X
X
L
L
L
H
L
BA
OP Code
OP Code
X
X
X
BA
X
BA
BA
BA
BA
X
5
6
H
X
X
X
L
H
L
H
X
L
H
X
L
H
X
X
L
H
L
H
L
H
X
L
H
X
X
X
L
H
L
H
L
X
H
H
H
H
H
H
L
L
L
L
L
X
X
X
NOP
ILLEGAL
2
2
6
3
CA, AP Begin Read ; Latch CA ; Determine AP
ILLEGAL
X
Row
Active
CA, AP Begin Write ; Latch CA ; Determine AP
CA, AP Begin Write ; Latch CA ; Determine AP
RA
RA
X
ILLEGAL
Precharge
ILLEGAL
ILLEGAL
X
X
X
X
ILLEGAL
L
OP Code
X
X
X
X
Special Mode Register Access
NOP (Continue Burst to End
NOP (Continue Burst to End
Term burst Row active
ILLEGAL
X
H
H
H
H
H
H
H
L
X
X
X
X
Row Active)
Row Active)
BA
X
CA, AP Term burst, Begin Read ; Latch CA ; Determine AP
Read
X
ILLEGAL
Term burst, Begin Write ; Latch CA ; Determine AP
Term burst, Begin Write ; Latch CA ; Determine AP
BA
BA
BA
BA
X
X
X
X
X
X
BA
X
BA
BA
CA, AP
CA, AP
RA
PA
X
3
3
2
3
ILLEGAL
L
L
L
Term Burst, Precharge timing for Reads
ILLEGAL
ILLEGAL
X
X
X
X
X
H
H
H
H
H
H
H
NOP (Continue Burst to End
NOP (Continue Burst to End
Row Active)
Row Active)
Term burst
ILLEGAL
Row Active
Write
X
CA, AP Term burst, Begin Read ; Latch CA ; Determine AP
3
X
ILLEGAL
Term burst, Begin Write ; Latch CA ; Determine AP
Term burst, Begin Write ; Latch CA ; Determine AP
CA, AP
CA, AP
3
3
H
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 30/54