M32L1632512A
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh (2K cycles) is recommended.
12. About Burst Type Control
At MRS A3=”0”. See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page wrap around.
Sequential Counting
Interleave Counting
Basic
Mode
At MRS A3=”1”. See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
At MRS A3=”1”. (See to interleave Counting Mode)
Staring Address LSB 3 bits A 0-2 should be “000” or “111”. @BL=8
- if LSB =”000” : Increment Counting.
- if LSB =”111” : Decrement Counting.
Pseudo-
Document Sequential
Counting
For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)
-- @ write, LSB =”000”, Accessed Column in order 0-1-2-3-4-5-6-7
-- @ read, LSB =”111”, Accessed Column in order 7-6-5-4-3-2-1-0
At BL=4, same applications are possible. As above example, at interleave Counting
mode, by confining starting address to some value, Pseudo-Decrement Counting
Mode can be realize. See the BURST SEQUENCE TABLE carefully.
Pseudo-
MODE
At MRS A3=”0”. (See to Sequential Counting Mode)
A0-2 =”111”. (See to Full Page Mode)
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be
realize.
-- @ Sequential Counting, Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8)
-- @ Pseudo-Binary Counting
Pseudo-
Binary Counting
Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)
Note. The next column address of 256 is 0.
Random column
Access
Every cycle Read/Write Command with random column address can realize
Random Column Access
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random
MODE
tCCD = 1 CLK
13. About Burst Length Control
At MRS A2, 1, 0 =”000”.
1
At auto precharge, tRAS should not be violated.
Basic
MODE
At MRS A2, 1, 0 =”001”.
2
At auto precharge, tRAS should not be violated.
4
8
At MRS A2, 1, 0 =”010”.
At MRS A2, 1, 0 =”011”.
At MRS A2, 1, 0 =”111”.
Full Page
Wrap around mode (Infinite burst length) should be stopped by burst stop.
RAS interrupt or CAS interrupt.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
26/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
