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M32L1632512A-8Q 参数 Datasheet PDF下载

M32L1632512A-8Q图片预览
型号: M32L1632512A-8Q
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 512KX32, 6.5ns, CMOS, PQFP100,]
分类和应用: 时钟动态存储器内存集成电路
文件页数/大小: 54 页 / 877 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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M32L1632512A  
FUNCTION TRUTH TABLE (TABLE 1, Continued)  
*Note : 1. All entries assume the CKE was active (High) during the preceding clock cycle and the current clock cycle.  
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that  
bank.  
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).  
5. Illegal if any bank is not idle.  
6. Legal only if all banks are in idle or row active state.  
FUNCTION TRUTH TABLE for CKE (TABLE2)  
Current  
State  
CKE CKE  
DSF ADDR  
ACTION  
Note  
CS RAS CAS WE  
( n-1 )  
n
H
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
INVALID  
7
7
Exit Self Refresh  
after tRC  
after tRC  
Self  
L
H
L
H
H
H
X
X
Exit Self Refresh  
ILLEGAL  
ILLEGAL  
ILLEGAL  
NOP (Maintain Self Refresh)  
INVALID  
Exit Power Down ABI  
Exit Power Down ABI  
ILLEGAL  
ILLEGAL  
ILLEGAL  
NOP (Maintain Low Power Mode)  
Refer to Table 1  
Enter Power Down  
Enter Power Down  
ILLEGAL  
ILLEGAL  
ILLEGAL  
Enter Self Refresh  
ILLEGAL  
NOP  
Refresh  
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
H
L
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
Both  
Bank  
Precharge  
Power  
8
8
Down  
9
9
All  
Banks  
Idle  
L
L
9
X
X
X
X
X
Any State  
other than  
Listed  
Refer to Operations in Table 1  
Begin Clock Suspend next cycle  
Exit Clock Suspend next cycle  
Maintain Clock Suspend  
10  
10  
Above  
ABBREVIATIONS : ABI = All Banks Idle  
*Note : 7.After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to  
high transition to issue a new command.  
8.CKE low to high transition is asynchronous as if restart internal clock.  
A minimum setup time “ tSS + one clock “ must be satisfy before any command other than exit.  
9.Power down and self refresh can be entered only from the all banks idle state.  
10.Must be a legal command.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2001  
Revision : 1.6 32/54  
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