M32L1632512A
3) Read (BL=4)
C L K
C M D
R D
D Q ( C L 2 )
D Q ( C L 3 )
Q 0
Q 2
Q 1
Q 3
Q 1
Q 0
Q 2
Q 3
* N o t e 3
A u t o P r e c h a r g e s t a r t s
*Note : 1. tRDL : Write data-in to PRE command delay, tBPL : Block Write data-in to PRE command delay.
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same bank is illegal.
4. For -5S/-6S/-7S/-8S, auto precharge after a normal write starts at clock(n+BL+1).
8. Burst Stop & Precharge Interrupted
1) Write interrupted by Precharge (BL=4)
2) Write Burst Stop (Full Page Only)
C L K
C M D
C L K
C M D
S T O P
P R E
W R
W R
D Q M
D Q
D Q
D 3
D 0
D 2
D 0
D 1
D 1
D 2
* N o t e 1
t B D L
t R D L
3) Read interrupted by Precharge (BL=4)
4) Read Burst Stop (Full Page Only)
C L K
C M D
C L K
C MD
D Q (C L2 )
D Q (C L3 )
S TO P
Q 0
R D
R D
P R E
Q 0
* N o t e 3
1
* N o t e 3
1
Q 1
Q 0
Q 1
Q 0
D Q (C L2 )
D Q (C L3 )
2
2
Q 1
Q 1
9. MRS & SMRS
1) Mode Register Set
2) Special Mode Register Set
C L K
C M D
C L K
* N o t e 4
C M D
P R E
S M R S AC T
S M R S
AC T
S M R S AC T
M R S
1 C L K
1 C L K
1 C L K
1 C L K
1 C L K
t R P
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 24/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
