M32L1632512A
*Note: 1. tRDL : 1 CLK ; Last data in to Row Precharge.
2. tBDL : 1 CLK ; Last data in to Burst Stop Delay.
3. Number of valid output data after Row Precharge or burst stop : 1, 2 for CAS latency = 2, 3 respectively.
4. PRE : Both banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
10. Clock Suspend Exit & Power Down Exit
1) Clock Supend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
C L K
C L K
C K E
C K E
t S S
t S S
I n t e r n a l
C L K
I n t e r n a l
* N o t e 1
* N o t e 2
C LK
R D
C M D
AC T
C MD
N O P
11. Auto Refresh & Self Refresh
*Note3
1) Auto Refresh
C L K
* N o t e 4
* N o t e 5
C MD
C K E
AR
P R E
C M D
t R P
t R C
*Note6
1) Self Refresh
C L K
C M D
* N o t e 4
P R E
C M D
S R
C K E
t R P
t R C
*Note 1. Active power down : one or more banks active state.
:
2. Precharge power down : both banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 25/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
