M32L1632512A
3.
Interrupt (I)
CAS
* N o t e 1
1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 )
C L K
C M D
AD D
R D
A
R D
B
Q A0
D Q ( C L2 )
D Q ( C L 3 )
Q B 1 Q B 2 Q B 3
Q B 0
Q A0
Q B 0 Q B 1
Q B 3
Q B 2
t C C D
* N o t e
2
2 ) W r i t e i n t e r r u p t e d b y ( B l o c k ) W r i t e ( B L = 2 )
3 ) W r i t e i n t e r r u p t e d b y R e a d ( B L = 2 )
C L K
B W
W R
R D
C M D
W R
W R
W R
t C C D
t C C D
* N o t e
2
* N o t e 2
t C C D
* N o t e
2
A
B
A
A
AD D
D Q
B
B
* N o t e
4
D A0
D A0
D B 1
P i x e l
D B 0
D A0 D B 0
D C 0
D B 1
D Q ( C L 2 )
D Q ( C L 3 )
t C D L
t C D L
D B 0 D B 1
* N o t e
3
* N o t e
3
t C D L
* N o t e
3
4 ) B l o c k W r i t e t o B l o c k W r i t e
C L K
N O P
B W
B
B W
C M D
AD D
N o t e
7
A
X
N o t e
4
P i x e l
P i x e l
D Q
t B W C
* N o t e
6
*Note : 1. By “Interrupt”, It is possible to stop burst read/write by external before the end of burst.
By “ CAS Interrupt”, to stop burst read/write by CAS access ; read, write and block write.
2.tCCD : CAS to CAS delay.(=1CLK)
3.tCDL : Last Data in to new column address delay.(=1CLK)
4.Pixel : Pixel mask.
5.tCC : Clock cycle time.
6.tBWC : Block write minimum cycle time.
7.Other Bank can be active or precharge.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 21/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
