M32L1632512A
Test Mode
Type
CAS Latency
Burst Type
Type
Burst Length
A8
0
A7
0
A6
0
A5
0
A4 Latency A3
A2
0
A1
0
A0
0
BT = 0
BT = 1
Reserved
Reserved
4
Mode Register Set
0
1
0
1
0
1
0
1
Reserved
-
0
Sequential
1
2
4
8
0
1
Vendor
Use
0
0
1
Interleave
0
0
1
1
0
0
1
2
0
1
0
1
1
Only
0
1
3
0
1
1
8
Write Burst Length
Length
1
0
Reserved
Reserved
Reserved
Reserved
1
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
256(Full) Reserved
(Note 3)
A9
0
1
0
1
0
1
Burst
1
1
1
1
0
1
Single Bit
1
1
1
1
1
Special Mode Register Programmed with SMRS
Address
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A
Function
X
LC
LM
X
Load Color
Load Mask
A6
0
Function
A5
Function
Disable
Enable
Disable
Enable
0
1
1
(Note 4)
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP
condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µ s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256bit) is available only at Sequential mode of burst type.
4. If LC and LM both high (1), data of mask and color register will be unknown.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 11/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
