M32L1632512A
SIMPLIFIED TRUTH TABLE
COMMAND
Mode Register set
CKEn-1 CKEn
DSF DQM A10 A9 A8~A0
Note
CS
WE
RAS CAS
L
1, 2
Register
Refresh
H
H
L
X
L
L
L
L
L
L
X
X
X
X
OP CODE
1, 2, 7
Special Mode Register Set
Auto Refresh
H
H
L
3
3
L
H
L
X
Entry
Self
L
H
X
H
X
H
X
3
Refresh
Exit
H
X
X
X
H
3
L
Write Per Bit Disable
Write Per Bit Enable
4, 5
Bank Active
& Row Addr.
H
L
L
H
H
V
Row Address
H
4,5,9
4
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
Column
Address
Read & Column
Address
H
H
X
X
L
L
H
H
L
L
H
L
L
L
X
X
V
V
V
4, 6
4, 5
4,5,6,9
4, 5
4,5,6,9
7
Write & Column
Address
Column
Address
H
L
Block Write &
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
H
L
L
X
X
X
Column Address
H
Burst Stop
Precharge
X
Bank Selection
Both Banks
V
X
L
X
H
L
H
X
L
H
X
X
H
X
H
X
X
H
X
H
X
X
H
X
H
L
L
H
L
Clock Suspend or
Active Power Down
Entry
Exit
X
X
X
X
X
X
X
X
Entry
H
H
Precharge Power Down Mode
L
V
X
V
X
V
X
V
X
X
V
X
Exit
L
H
X
H
DQM
H
X
H
X
X
8
L
H
X
H
X
H
X
No Operation Command
H
X
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low )
Note : 1.OP Code : Operand Code
A0~A10 : Program keys. (@ MRS)
A5, A6 : LMR & LCR select. (@ SMRS)
Color register exists only one per DQi which both banks share.
So does Mask Register.
Color or mask is loaded into chip through DQ pin.
2.MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ’s are idle.
A new command can be issued at the next clock of MRS/SMRS.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 9/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
