M32L1632512A
DEVICE OPERATIONS (Continued)
burst type as the default value of mode register is
undefined.
BANK ACTIVATE
The bank activate command is used to select a
random row in an idle bank. By asserting low
At the end of one clock cycle from the mode
register set cycle, the device is ready for operation.
When the above sequence is used for Power-up, all
the outputs will be in high impedance state. The
high impedance of outputs is not guaranteed in any
other power-up sequence.
on RAS and CS with desired row and bank
addresses, a row access is initiated. The read or
write operation can occur after a time delay of
tRCD (min) from the time of bank activation. tRCD
(min) is the internal timing parameter of SGRAM,
therefore it is dependent on operating clock
frequency. The minimum number of clock
cycles required between bank activate and read
or write command should be calculated by
dividing tRCD (min) with cycle time of the clock
and then rounding of the result to the next
higher integer. The SGRAM has two internal
banks in the same chip and shares part of the
internal circuitry to reduce chip area, therefore
it restricts the activation of both banks
immediately. Also the noise generated during
sensing of each bank of SGRAM is high
requiring some time for power supplies to
recover before another bank can be sensed
reliably. tRRD (min) specifies the minimum time
required between activating different bank. The
number of clock cycles required between
different bank activation must be calculated
similar to tRCD specification. The minimum time
required for the bank to be active to initiate
sensing and restoring the complete row of
dynamic cells is determined by tRAS (min). Every
SGRAM bank activate command must satisfy
tRAS (min) specification before a precharge
command to that active bank can be asserted.
The maximum time any bank can be in the
active state is determined by tRAS (max). The
number of cycles for both tRAS(min) and tRAS
(max) can be calculated similar to tRCD
specification.
cf.) Sequence of 4 & 5 may be changed.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SGRAM. It programs
the CAS latency, burst type, addressing, burst
length, test mode and various vendor specific
options to make SGRAM useful for variety of
different applications. The default value of the
mode register is not defined, therefore the mode
register must be written after power up to operate
the SGRAM. The mode register is written by
asserting low on CS, RAS , CAS, WE and
DSF (The SGRAM should be in active mode with
CKE already high prior to writing the mode
register). The state of address pins A0~A9 and A10
in the same cycle as CS, RAS , CAS, WE and
DSF going low is the data written in the mode
register. One clock cycles is required to complete
the write in the mode register. The mode register
contents can be changed using the same command
and clock cycle requirements during operation as
long as both banks are in the idle state. The mode
register is divided into various fields depending
on functionality. The burst length field uses
A0~A2, burst type uses A3, CAS latency (read
latency from column address) A4~A6, A7~A8 and
A10 are uses for vendor specific options or test
mode use. And the write burst length is
programmed using A9. A7~A8 and A10 must be
set to low for normal SGRAM operation. Refer to
the table for specific codes for various burst length,
BURST READ
addressing modes and CAS latencies.
The burst read command is used to access burst
of data on consecutive clock cycles from an
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
14/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
