M32L1632512A
*Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2 - 0.5) ns should be added to the parameter.
3. Assumed input rising and falling time (tr & tf) = 1ns.
If tr & tf is longer 1ns, transient time compensation should be considered.
i.e., [(tr + tf)/2 - 1] ns should be added to the parameter.
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-5
-5S
-6
-6S -7 -7S -8 -8S
Row active to row active delay
1
1
1
1
10
15
15
40
12
18
18
40
14
20
21
42
16
20
24
48
tRRD(min)
tRCD(min)
tRP(min)
ns
ns
RAS to CAS delay
Row precharge time
ns
tRAS(min)
tRAS(max)
tRC(min)
tCDL(min)
tRDL(min)
tBPL(min)
Row active time
us
100
Row cycle time
ns
1
2
2
55
60
63
72
Last data in to new col. address delay
Last data in to row precharge
Block write data-in to PRE command delay
CLK
CLK
ns
1
2
1
2
1
1
2
1
2
10
25
12
30
14
35
16
40
Block write data-in to Active (REF)
command period (Auto precharge)
Last data to burst stop
ns
tBAL(min)
CLK
CLK
CLK
2
3
4
1
1
tBDL(min)
tCCD(min)
tBWC(min)
Col. Address to col. Address delay
Block write cycle time
2
2
2
2
2
1
CAS latency = 3
CLK
5
Number of valid Output data
CAS latency = 2
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change except block write cycle.
4. This parameter means minimum CAS to CAS delay at block write cycle only.
5. In case of row precharge interrupt, auto precharge and read burst stop.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 7/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
