M32L1632512A
Page Read & Write Cycle Same Bank @ Burst Length = 4
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
6
8
4
5
7
C L O C K
H I G H
C K E
C S
tR C D
R A S
* N o t e 2
C A S
R a
Cb0
Cc 0
C d0
Ca0
A D D R
A10
A9
R a
tR D L
tC D L
W E
D S F
* N o t e 2
* N o t e 3
* N o t e 1
D Q M
DQ C L= 2
Qa0 Qa1 Qb0
Qb1
Qb0
Dc 0 Dc 1 Dd0 Dd1
CL = 3
D c 0
Dc 1 D d0
Dd1
Qa0
Qa1
Rea d
( A- Ban k )
Rea d
( A- Ban k )
Row Ac t i v e
( A- B an k )
W ri t e
(A - Ban k )
W r i te
(A- Ba n k )
Pre char ge
( A- B an k )
:D on' t C ar e
* Note : 1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, RDL before Row precharge, will be written.
t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 37/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
