M32L1632512A
* Note : 1. All input can be don’t care when
is high at the CLK high going edge.
CS
2. Bank active & read/write are controlled by A10.
A10
0
Active & Read/Write
Bank A
1
Bank B
3. Enable and disable auto precharge function are controlled by A9 in read/write command.
A9
0
A10
0
Operation
Disable auto precharge, leave bank A active at end of burst.
1
0
1
Disable auto precharge, leave bank B active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
1
4. A9 and A10 control bank precharge when precharge command is asserted.
A9
0
A10
0
Precharge
Bank A
0
1
Bank B
1
X
Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.
A10
0
DSF
L
Operation
Bank A row active, disable write per bit function for bank A.
H
L
Bank A row active, enable write per bit function for bank A.
Bank B row active, disable write per bit function for bank B.
Bank B row active, enable write per bit function for bank B.
1
H
6. Block write/normal write is controlled by DSF.
DSF
L
Operation
Minimum cycle time
Normal write
t
CCD
H
Block write
t
BWC
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 35/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
