M32L1632512A
Read & Write Cycle at Same Bank @ Burst Length = 4
11
12
13
15
17
19
1
2
3
9
10
14
16
18
0
6
8
4
5
7
C L O C K
H I G H
C K E
* N o t e 1
tR C
C S
R C D
t
R A S
* N o t e 2
C A S
R a
R b
C b0
C a0
A D D R
A10
A9
R a
R b
W E
D S F
D Q M
tO H
Qa3
DQ C L = 2
D b0 D b1
Qa0 Qa1
D b2 Db3
Qa2
tR A C
R D L
t
* N o t e 3
* N o t e 4
S A C
t
S H Z
t
tO H
C L = 3
Qa3
Qa0
Qa1 Qa2
Db0
Db1 Db2 Db3
R A C
* N o t e 3
t
tR D L
*N o t e 4
tS A C
tS H Z
R ea d
(A - Ban k )
R ow A c t i v e
( A- B an k )
Prec ha rg e
( A- B an k )
W r i te
(A - Ba n k )
R ow A c t i v e
( A- Ban k )
Pre ch arg e
( A- B an k )
: D on ' t C ar e
*Note :
1. Minimum row cycle time is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle.[CAS Length - 1] valid output data available after Row. enters precharge. Last valid output will be
Hi-Z after tSHZ
from the clock.
3. Access time from Row address. tCC *( tRCD +CAS latency - 1) + tSAC
4. Output will be Hi-Z after the end of burst. (1, 2, 4 & 8)
At Full page bit burst, burst is wrap-around.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6 36/54
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
