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M24L816512SA-55BEG 参数 Datasheet PDF下载

M24L816512SA-55BEG图片预览
型号: M24L816512SA-55BEG
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 512K ×16 )伪静态RAM [8-Mbit (512K x 16) Pseudo Static RAM]
分类和应用:
文件页数/大小: 14 页 / 328 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M24L816512SA  
Switching Characteristics (Over the Operating Range) (continued)[10, 11, 12, 13, 14]  
-55  
-70  
Parameter  
Description  
Write Cycle Time  
Unit  
Min.  
Max.  
Min.  
Max.  
Write Cycle[13]  
tWC  
55  
45  
70  
55  
ns  
ns  
tSCE  
CE LOW to Write End  
tAW  
tHA  
tSA  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
45  
0
0
55  
0
0
ns  
ns  
ns  
tPWE  
tBW  
40  
50  
42  
0
55  
55  
42  
0
ns  
ns  
ns  
ns  
ns  
ns  
WE Pulse Width  
BLE /BHE LOW to Write End  
Data Set-up to Write End  
tSD  
tHD  
Data Hold from Write End  
tHZWE  
tLZWE  
25  
25  
WE LOW to High-Z[11, 12]  
WE HIGH to Low-Z[11, 12]  
5
5
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)[14, 15, 16]  
Read Cycle 2 (OE Controlled)[14, 15]  
Notes:  
15. WE is HIGH for Read Cycle.  
16. Device is continuously selected. OE , CE = VIL  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2009  
Revision : 1.5 6/14  
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