欢迎访问ic37.com |
会员登录 免费注册
发布采购

M24L816512SA-55BEG 参数 Datasheet PDF下载

M24L816512SA-55BEG图片预览
型号: M24L816512SA-55BEG
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 512K ×16 )伪静态RAM [8-Mbit (512K x 16) Pseudo Static RAM]
分类和应用:
文件页数/大小: 14 页 / 328 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号M24L816512SA-55BEG的Datasheet PDF文件第5页浏览型号M24L816512SA-55BEG的Datasheet PDF文件第6页浏览型号M24L816512SA-55BEG的Datasheet PDF文件第7页浏览型号M24L816512SA-55BEG的Datasheet PDF文件第8页浏览型号M24L816512SA-55BEG的Datasheet PDF文件第10页浏览型号M24L816512SA-55BEG的Datasheet PDF文件第11页浏览型号M24L816512SA-55BEG的Datasheet PDF文件第12页浏览型号M24L816512SA-55BEG的Datasheet PDF文件第13页  
ESMT  
M24L816512SA  
Avoid Timing  
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal  
shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during  
15μs shown as in Avoidable timing 1 or toggle CE to high (tRC) one time at least shown as in Avoidable Timing 2.  
Abnormal Timing  
15μ s  
CE  
WE  
tRC  
Address  
Avoidable Timing 1  
15μ s  
CE  
WE  
tRC  
Address  
Avoidable Timing 2  
15μ s  
CE  
tRC  
WE  
tRC  
Address  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Jun. 2009  
Revision : 1.5 9/14  
 复制成功!