ESMT
Preliminary
M24L16161A
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
t
WC
Address
CE1
t
AW
t
CW
3
t
WR
1
2
tBW
t
AS
HB, LB
WE
t
WP
t
DH
t
DW
DATA IN
4
WHZ
t
t
OW
DATA OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE1 , WE and (HB and , or LB ).
3. tWR is measured from the earliest of CE1 or WE or (HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2 9/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
