ESMT
Preliminary
M24L16161A
Avoid Timing
ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address
signal shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at
leat during 15μs shown as in Avoidable timing 1 or toggle CE1 to high (≧tRC) one time at least shown as in Avoidable
Timing 2.
Abnormal Timing
≧
μ
15
s
CE1
WE
＜
t
RC
Address
Avoidable Timing 1
≧
μ
15
s
CE1
WE
≧
t
RC
Address
Avoidable Timing 2
≧
μ
15
s
CE1
WE
≧
t
RC
＜
t
RC
Address
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2 13/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
