ESMT
Timing Waveforms
Read Cycle - Addressed Controlled
Preliminary
M24L16161A
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
Read Cycle - CE1 Controlled
t
RC
Address
t
AA
CE1
t
ACE1
t
CLZ5
HB, LB
t
BLZ5
t
BE
t
CHZ5
5
t
BHZ
OE
t
OE
5
t
OLZ
5
t
OHZ
D
OUT
Notes:
1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = V
IL
, HB = V
IL
and, or LB = V
IL
.
3. Address valid prior to or coincident with CE1 and ( HB and, or LB ) transition low.
4. OE = V
IL
.
5. Transition is measured
±500mV
from steady state. This parameter is sampled and not 100% tested.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2003
Revision : 0.2
6/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
