ESMT
M13S5121632A
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the
interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C L K
C L K
1tC K
NO P
WRITE A
NO P
NO P
NO P
NO P
NO P
NO P
WRITE B
C O M M A N D
DQ S
Din A0
Din B0
Din B1
Din B2
Din B3
Din A1
D Q ' s
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Read burst, a Burst Terminate command is required to stop the read burst
and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum
delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write command to interrupt a Read with autoprecharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0 19/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
