ESMT
M13S5121632A
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge
enabled after tDQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C L K
C L K
NO P
NO P
W R I T E
NO P
NO P
NO P
NO P
NO P
NO P
C O M M A N D
t D S H
tD S S
tD Q S S
tW P S T
DQ S
tW P R E S
D i n 2 D i n 3
D i n 1
D i n 0
D Q ' s
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0 16/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
