ESMT
M13S5121632A
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
R E A D
B
N O P
N O P
N O P
N O P
N O P
R E A D
A
N O P
N O P
C O M M A N D
D Q S
C A S L a t e n c y = 3
Dout
B0
Dout
D Q ' s
Dout
A
0
Dout
A
1
B1 Dout B2 Dout B3
Read Interrupted by a Write & Burst Stop
To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s(Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks ［RU means round up to the nearest integer］ before
the Write command.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
Bu r st St op
NO P
NO P
NO P
NO P
R E A D
NO P
W R I T E
NO P
C O M M A N D
DQ S
C A S L a t e n c y = 3
Dout
0
Dout
1
Din 0
Din 3
Din 1 Din 2
D Q ' s
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0 17/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
