ESMT
IDD Specifications
Symbol
-4
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Version
-5
75
71
10
29
28
15
43
97
90
192
10
290
M13S5121632A (2R)
Unit
-6
67
63
9
27
27
14
39
88
76
112
9
250
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Input / Output Capacitance
Parameter
Input capacitance (A0~A12, BA0~BA1,
CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Package
TSOP
Symbol
C
IN1
Min
2.0
Max
3.0
Delta Cap
(max)
0.5
Unit
pF
Note
1,4
TSOP
C
IN2
2.0
3.0
0.25
pF
1,4
Data & DQS input/output capacitance
TSOP
C
OUT
4.0
5.0
0.5
pF
1,2,3,4
Input capacitance (DM)
TSOP
C
IN3
4.0
5.0
0.5
pF
1,2,3,4
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. V
DDQ
= 2.5V
±
0.2V, V
DD
= 2.5V
±
0.2V for speed grade -5 and -6. V
DDQ
= 2.6V
±
0.1V,
V
DD
= 2.6V
±
0.1V for speed grade -4. f=100MHz, T
A
=25°C, V
OUT
(DC) = V
DDQ
/2, V
OUT
(peak to peak) = 0.2V. DM
inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the
board level).
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2013
Revision : 1.3
7/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
