ESMT
AC Timing Parameter & Specifications
(Note: 1~5)
Parameter
CL2
Clock period
CL2.5
CL3
DQ output access time from CLK/ CLK
CLK high-level width
CLK low-level width
DQS output access time from
CLK/ CLK
Clock to first rising edge of DQS delay
DQ and DM input setup time (to DQS)
DQ and DM input hold time (to DQS)
DQ and DM input pulse width (for each
input)
Address and Control input setup time
(fast)
Address and Control input hold time
(fast)
Address and Control input setup time
(slow)
Address and Control input hold time
(slow)
Control and Address input pulse width
(for each input)
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Data strobe edge to output data edge
Data-out high-impedance time from
CLK/ CLK
Data-out low-impedance time from
CLK/ CLK
Clock half period
DQ/DQS output hold time from DQS
Data hold skew factor
t
AC
t
CH
t
CL
t
DQSCK
t
DQSS
t
DS
t
DH
t
DIPW
t
IS
t
IH
t
IS
t
IH
t
IPW
t
DQSH
t
DQSL
t
DSS
t
DSH
t
DQSQ
t
HZ
t
LZ
-0.7
t
CL
min
or
t
CH
min
t
HP
- t
QHS
0.4
t
CK
Symbol
Min
7.5
6
4
-0.7
0.45
0.45
-0.7
0.85
0.4
0.4
1.75
0.6
0.6
0.7
0.7
2.2
0.4
0.4
0.2
0.2
0.4
+0.7
+0.7
-0.7
t
CL
min
or
t
CH
min
t
HP
- t
QHS
-4
max
12
12
7.5
+0.7
0.55
0.55
+0.7
1.15
min
7.5
6
5
-0.7
0.45
0.45
-0.6
0.72
0.4
0.4
1.75
0.6
0.6
0.7
0.7
2.2
0.35
0.35
0.2
0.2
M13S5121632A (2R)
-5
max
12
12
7.5
+0.7
0.55
0.55
+0.6
1.25
min
7.5
6
-
-0.7
0.45
0.45
-0.6
0.75
0.45
0.45
1.75
0.75
0.75
0.8
0.8
2.2
0.35
0.35
0.2
0.2
0.4
+0.7
+0.7
-0.7
t
CL
min
or
t
CH
min
t
HP
- t
QHS
0.5
-6
max
12
12
-
+0.7
0.55
0.55
+0.6
1.25
Unit
Note
ns
8
ns
t
CK
t
CK
ns
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
9
9
10
10,
15~17
10,
15~17
10,
16~18
10,
16~18
10
0.45
+0.7
+0.7
ns
ns
ns
11
11
t
HP
t
QH
t
QHS
ns
ns
0.55
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2013
Revision : 1.3
9/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
