ESMT
IDD Parameters and Test Conditions
Test Condition
M13S5121632A (2R)
Symbol
IDD0
IDD1
IDD2P
Note
1,2
1,2
1
Operating Current (one bank Active - Precharge):
t
RC
= t
RC
(min); DQ, DM, and DQS inputs changing twice per clock cycle; Address and control inputs
changing once per clock cycles.
Operating Current (one bank Active - Read - Precharge):
BL = 2; t
RC
= t
RC
(min); I
OUT
= 0mA; CL=2.5; Address and control inputs changing once per deselect cycle.
Precharge Power-down Standby Current:
All banks idle; Power-down mode; CKE
V
IL
(max).
Idle Standby Current:
CS
V
IH
(min); All banks idle; CKE
V
IH
(min); Address and other control inputs changing once per clock
cycle.
Precharge Floating Standby Current:
CS
V
IH
(min); All banks idle; CKE
V
IH
(min); Address and other control inputs changing once per clock
cycle.
Active Power-down Standby Current:
One bank active; Power-down mode; CKE
V
IL
(max).
Active Standby Current:
CS
V
IH
(min); CKE
V
IH
(min); One bank active - precharge; t
RC
= t
RAS
(max); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs changing once per clock cycle.
Operating Current (burst read):
BL = 2; Continuous burst reads; One bank active;
Address and control inputs changing once per clock cycle; I
OUT
= 0mA; CL=2.5; DQ and DQS outputs
changing twice per clock cycle.
Operating Current (burst write):
BL = 2; Continuous burst writes; One bank active;
Address and control inputs changing once per clock cycle; CL=2.5; DQ and DQS inputs changing twice
per clock cycle.
Auto Refresh Current:
t
RC
= t
RFC
(min)
Self Refresh Current:
CKE
0.2V
Operating Current (Four bank operation):
Four-bank interleaving (burst = 4); t
RC
= t
RC
(min); Address and control inputs randomly changing; 50% of
data changing at every transfer; I
OUT
= 0mA.
Notes:
1. IDD specifications are tested after the device is properly initialized.
2. Enable on-chip refresh and address counters. Values are averaged from high and low temp values.
IDD2F
1
IDD2Q
1
IDD3P
1
IDD3N
1,2
IDD4R
1,2
IDD4W
1,2
IDD5
IDD6
1
1
IDD7
1,2
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2013
Revision : 1.3
6/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
