ESMT
M13S32321A (2G)
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval
that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are
overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
0
1
2
3
4
5
6
7
8
C L K
C L K
1
t C K
W RITE A
W RITE B
NO P
NO P
NO P
N O P
CO MMA ND
N OP
N OP
N OP
Hi - Z
Hi- Z
DQ S
DIN A0
DIN A1
DIN B0
DIN B1
DIN B2
DIN B3
DQ ' s
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0 21/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
