ESMT
M13S32321A (2G)
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is tCCD(min).
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
t C CD ( mi n )
RE A D B
NO P
NO P
NOP
NO P
NO P
CO MMA ND
RE A D A
NO P
N OP
Hi -Z
DQ S
DOUT B0 DOUT B 1 DOUT B2 DOUT B3
DOUT A0 DOUT A1
DQ ' s
Hi- Z
Read Interrupted by a Write & Burst Terminate
To interrupt a burst read with a write command, Burst Terminate command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s (Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks [RU mean round up to the nearest integer] before the
Write command.
<Burst Length = 4, CAS Latency = 3>
0
1
2
3
4
5
6
7
8
C L K
C L K
Burs t
Term i nate
N O P
N O P
R E A D
N O P
W R I T E
N O P
N O P
C O M M A N D
N O P
D Q S
D
OUT 0
OUT 1
DIN 2
D
D
IN
0
D
IN
1
DIN 3
D Q ' s
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write
command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0 19/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
