ESMT
M13S32321A (2G)
Read with Auto Precharge
If a read with auto precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later
from a read with auto precharge command when tRAS (min) is satisfied. If not, the start point of precharge operation will be delayed
until tRAS (min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not
be asserted until the precharge time (tRP) has been satisfied.
<Burst Length = 4, CAS Latency = 2 & 2.5>
0
1
2
3
4
5
6
7
8
9
C L K
C L K
Read A
C O M M A N D
Bank A
ACTIVE
N O P
N O P
N O P
N O P
N O P
N O P
N O P
N O P
Auto Precharge
t
R A S ( m i n )
D Q S
H i - Z
H i - Z
CAS Latency = 2
D
DOUT 0
OUT 1
D
OUT 2
D
OUT 3
D Q ' s
D Q S
* Bank can be reactivated at
completion of precharge
t
R P
H i - Z
H i - Z
CAS Latency = 2.5
D
OUT 0
OUT 1
D
OUT 2 DOUT 3
D
D Q ' s
Auto-Precharge starts
When the Read with Auto Precharge command is issued, new command can be asserted at 4, 5 and 6 respectively as follow.
For the same bank
For the different bank
Asserted
Command
4
5
6
4
5
6
READ
READ
Illegal
Illegal
Illegal
Legal
Illegal
Illegal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
Legal
READ with AP*1 READ with AP
Active
Illegal
Legal
Precharge
Note 1: AP = Auto Precharge
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0 25/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
