ESMT
M13S32321A (2G)
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each
bank respectively or all banks simultaneously. The bank select address (BA) is used to define which bank is precharged when the
command is initiated. For write cycle, tWR(min) must be satisfied until the precharge command can be issued. After tRP from the
precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by bank address bits
A8/AP
BA
0
Precharge
Bank A Only
Bank B Only
All Banks
0
0
1
1
X
No Operation & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP the device should finish the current operation when this command is issued.
Bank / Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock
(CLK). The DDR SDRAM has two independent banks, so Bank Select address (BA) is required. The Bank Activation command must
be applied before any Read or Write operation is executed. The Bank Activation command to the first Read or Write command must
meet or exceed the minimum of RAS to CAS delay time (tRCDRD or tRCDWR min). Once a bank has been activated, it must be
precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between
interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
Tn
Tn+1
Tn+2
0
1
2
3
C L K
C L K
B a n k
A
B a n k
A
B ank
A
B a n k
B
A d d r e s s
R o w A d d r .
C o l . A d d r .
Row. Ad dr.
R o w A d d r .
R A S - C A S d e l a y
(
t R C D W R
)
R A S - R A S d e l a y
(
t R R D
)
W r i t e
A
B a n k
A
B a n k
B
B a n k
A
N O P
C o m m a n d
N O P
N O P
w i t h A P
A c t i v a t e
A c t i v a t e
A c t i v a t e
R O W C y c l e T i m e
(
t R C )
: D o n ' t C a r e
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0 17/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
