ESMT
M13S32321A (2G)
Burst Terminate
The burst terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The burst terminate command has the fewest restrictions making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst terminate command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
burst terminate command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
0
1
2
3
4
5
6
7
8
C L K
C L K
Burst
Terminate
N O P
N O P
N O P
R E A D
A
N O P
C O MM A N D
N O P
N O P
N O P
The burst read ends after a deley equal to the CAS lantency.
D Q S
H i - Z
H i - Z
D
OUT 0
OUT 1
D Q ' s
D
The Burst Terminate command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with auto precharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the clock
edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data
mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
0
1
2
3
4
5
6
7
8
C L K
C L K
C O MM A N D
N O P
N O P
N O P
N O P
N O P
N O P
N O P
W R I T E
t
N O P
D Q S S
D Q S
D Q ' s
D M
H i - Z
H i - Z
D
IN
2
D
IN
5
DIN 6
D
IN
1
D
IN
3
D
I N
4
DIN 7
D
IN 0
t
DS
t
DH
m a s k e d b y D M = H
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2012
Revision : 1.0 24/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
