ESMT
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the register is not defined, therefore the mode register must be written after
EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE
and BA0~BA1 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register).
The state of address pins A0~A12 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the
mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle
state. The mode register is divided into various fields depending on functionality. The burst length uses A0~A2, addressing
mode uses A3, CAS latency (read latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL
reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing
modes and CAS latencies.
BA1 BA0 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
Burst Length
0
0
RFU
DLL
TM
Mode Register
CAS Latency
A8
0
DLL Reset
No
A7
0
Mode
Normal
Test
A3
0
Burst Type
Sequential
Interleave
1
Yes
1
1
Burst Length
A2 A1 A0
Length
CAS Latency
A6 A5 A4
Latency
Reserved
Reserved
Reserved
3
Sequential Interleave
BA1 BA0
Operating Mode
MRS Cycle
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved Reserved
0
0
0
1
2
4
8
2
4
8
EMRS Cycle
4
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
2.5
Reserved
Note: RFU (Reserved for future use) must stay “0” during MRS cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0 14/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
