ESMT
Read & Write Cycle at Different Bank @ Burst Length = 4
M12L128168A
0
1
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C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
C B c
CA a
R D b
C D b R B c
RA a
A13
A12
A10 /AP
CL = 2
RA a
RB b
R A c
* N o t e 1
tC D L
QAa1 QAa2
DD b2 DD d 3
QBc1
QBc0
QBc2
QBc1
QAa0
QAa3
DD b0 Ddb1
QBc 0
D Q
CL = 3
QAa1
Ddb1 DD b 2 DD d3
DD b 0
QAa0
QAa2 QAa3
W E
D Q M
Rea d
( B - Ban k )
W r i t e
( D - B a n k )
Ro w Ac t i ve
( A- B an k )
Read
( A - Ba n k )
Pr e ch ar ge
( A- B an k )
Row A c t i ve
( D - B a n k )
Row Active
(B-Bank)
: D o n ' t C a r e
*Note : 1. tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 34/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
