ESMT
Page Write Cycle at Different Bank @ Burst Length = 4
M12L128168A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
C S
R A S
* N o t e 2
C A S
A D D R
RA a
CA a
C D d
R C c
C C c
RB b
CB b
R D d
A1 3
A1 2
RA a
RB b
R C c
R D d
A10/AP
D Q
DD d 0
DD d1 CD d2
DAa0 DAa1 DAa2 DAa3
DBb1
D C c 1
DBb0
DBb2 DBb3 D C c 0
tR D L
tC D L
W E
* N o t e 1
D Q M
W r i t e
( D - B a n k )
R o w A c t i v e
( D - B a n k )
W r i t e
( A - B a n k )
W r i t e
( B - B a n k )
R o w A c t i v e
( A - Bank )
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
( B - B a n k )
W r i t e
( C - B a n k )
R o w A c t i v e
( C - B a n k )
:
D o n ' t c a r e
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 33/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
