ESMT
M12L128168A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H I G H
C K E
C S
tR C D
R A S
* N o t e 2
C A S
A D D R
C b
C a
C d
R a
C c
A13
A12
A10/AP
CL = 2
R a
tR D L
Dc 1
Dc 1
Dd1
Dd1
Qa0 Qa1
Qa0
Qb1 Qb2
Dd0
Dd0
Dc 0
Dc 0
Qb0
Qa1
D Q
CL = 3
Qb0
Qb1
tC D L
W E
* N o t e 1
* N o t e 3
D Q M
Read
( A - Bank )
Read
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
Row Active
( A - Bank )
Precharge
(A
- B an k )
: D o n ' t C a r e
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 31/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
