ESMT
Read & Write Cycle at Same Bank @ Burst Length = 4
M12L128168A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note1
tRC
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Ca
Cb
Rb
A13
A12
`
A10/AP
CL=2
Rb
Ra
tOH
Qa1
Db2
Qa0
Qa2
Qa3
Db1
Db0
Db0
Db3
tSHZ
Qa3
tRDL
tSAC
*Note3
DQ
tOH
Qa1
CL=3
Db3
Db2
Qa0
Db1
Qa2
*Note3
tRDL
tSAC
tSHZ
WE
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 30/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
