ESMT
M12L128168A
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
16
17
18
11
12
13
14
15
19
0
1
2
5
9
10
3
4
6
7
8
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
CA b
RA a
CA a
A13
A12
A10/AP
D Q
RA a
tR D L
tB D L
* N o t e 1
DAb0
DAa0 DAa1 DAa2
DAb2
DAa3 DAa4
DAb1
DAb3
DAb5
DAb4
W E
D Q M
W r i t e
(A - Ban k )
Burst Stop
Row A c t i ve
( A- B an k )
Precharge
( A- B an k )
W r i t e
( A - Ban k )
:D on' t C ar e
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2006
Revision: 2.0 38/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
