M11L416256A/M11L416256SA
CAPACITANCE
CC
(Ta = 25 , V = 3.3V ± 10%)
°C
PARAMETER
SYMBOL
TYP
MAX
5
UNIT
pF
I1
C
Input Capacitance (address)
-
-
-
WE
Input Capacitance (RAS , CASH , CASL ,
Output capacitance (I/O0~I/O15)
, OE )
I2
C
7
pF
I / O
C
10
pF
AC ELECTRICAL CHARACTERISTICS
CC
SS
(Ta = 0 to 70° , V =3.3V ± 10%, V = 0V) (note 14)
C
Test Conditions
Input timing reference levels : 0.8V, 2.0V
OL
OH
Output reference level : V = 0.8V, V =2.0V
Output Load : 2TTL gate + CL (50pF)
T
Assumed t = 2ns
-25
-28
-30
-35
-40
PARAMETER
SYMBOL
UNIT NOTES
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Read or Write Cycle Time
Read Write Cycle Time
RC
t
43
65
48
70
55
85
65
95
75
ns
ns
RWC
t
105
EDO-Page-Mode Read or Write Cycle
Time
PC
t
10
32
11
35
12
37
14
42
16
47
ns
ns
22
22
EDO-Page-Mode Read-Write Cycle
Time
PCM
t
RAC
t
Access Time From
Access Time From
Access Time From
25
8
28
9
30
9
35
10
40
11
ns
ns
4
RAS
CAS
OE
CAC
t
5,20
13,20
OAC
t
8
9
9
10
18
20
11
20
22
ns
ns
ns
Access Time From Column Address
Access Time From Precharge
AA
t
12
14
15
17
15
17
ACP
t
20
25
CAS
RAS
t
25
Pulse Width
30
30
9
35
35
10
25
5
40
40
11
30
6
ns
ns
ns
ns
ns
ns
ns
ns
RAS
RAS
RAS
RAS
CAS
CAS
CAS
RAS
CAS
10K
28
10K
10K
10K
10K
RASC
t
25 100K 28 100K
100K
100K
100K
Pulse Width (EDO Page Mode)
Hold Time
RSH
t
8
15
4
9
17
5
RP
t
Precharge Time
Pulse Width
20
5
CAS
t
10K
17
10K
19
24
19
10K
21
10K
25
10K
29
CSH
t
21
4
24
4
Hold Time
26
4
30
5
35
5
CP
Precharge Time
t
6,23
7,18
19
RCD
t
10
10
to
to
Delay Time
10
10
10
CAS
RAS
CRP
t
5
0
5
5
0
5
Precharge Time
5
0
5
8
5
0
5
8
5
0
5
8
ns
ns
ns
ns
Row Address Setup Time
Row Address Hold Time
ASR
t
RAH
t
RAD
t
8
0
5
13
8
0
5
13
to Column Address Delay Time
15
17
20
8
RAS
Column Address Setup Time
ASC
t
0
5
0
5
0
5
ns
ns
18
18
Column Address Hold Time
CAH
t
Column Address Hold Time (Reference
AR
t
22
24
26
30
34
ns
ns
to
)
RAS
RAL
t
12
0
15
0
Column Address to
Lead Time
15
0
18
0
20
0
RAS
Read Command Setup Time
15,18
RCS
t
Elite Memory Technology Inc
Publication Date: Agu. 2001
Revision : 1.3 4/16