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M11L416256SA-40T 参数 Datasheet PDF下载

M11L416256SA-40T图片预览
型号: M11L416256SA-40T
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 256KX16, 40ns, CMOS, PDSO40, TSOP2-44/40]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 16 页 / 230 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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M11L416256A/M11L416256SA  
Notes :  
1. Enables on-chip refresh and address counters.  
12. Those parameters are referenced to CAS leading  
WE  
edge in EARLY WRITE cycles and  
leading edge  
IH  
IL  
2. V (min) and V (max) are reference levels for  
in LATE WRITE or READ-MODIFY- WRITE cycles.  
measuring timing of input signals. Transition times  
IH  
IL  
are measured between V and V .  
13. During a READ cycle, if OE is low then taken HIGH  
before CAS goes high, I/O goes open, if OE is tied  
permanently low, a LATE WRITE or READ-MODIFY-  
WRITE operation is not possible.  
3. In addition to meet the transition rate specification, all  
IH  
IL  
input signals must transit between V and V in a  
monotonic manner.  
14. An initial pause of 200µ s is required after power-up  
followed by eight RAS refresh cycles (RAS only or  
CBR) before proper device operation is assured. The  
eight RAS cycle wake-ups should be repeated any  
REF  
RCD  
RCD  
RCD  
4. Assume that t  
< t (max). If t  
is greater than  
the maximum recommended value shown in this  
will increase by the amount that t  
exceeds the value shown.  
RAC  
RCD  
table, t  
time the t  
refresh requirement is exceeded.  
RCD  
RCD  
5. Assume that t  
t  
(max)  
WE  
15. WRITE command is defined as  
going low.  
6. If CAS is low at the falling edge of RAS , data-out  
will be maintained from the previous cycle. To initiate  
a new cycle and clear the data-out buffer, CAS and  
RAS must be pulsed high.  
16. LATE WRITE and READ-MODIFY-WRITE cycles must  
OEH  
have both tOFF2 and t  
met ( OE high during  
WRITE cycle) in order to ensure that the output buffers  
will be open during the WRITE cycles.  
RCD  
RCD  
7. Operation within the t  
limit ensures that t  
(max)  
OFF1  
OFF2  
17. The I/Os open during READ cycles once t  
occur.  
or t  
RCD  
can be met, t  
point only ; if t  
(max) is specified as a reference  
is greater than the specified t  
RCD  
RCD  
CAC  
(max) limit, access time is controlled by t  
.
18. Referenced to the earlier CAS falling edge.  
19. Referenced to the latter CAS rising edge.  
RAD  
RAD  
8. Operation within the t  
limit ensures that t (max)  
RAD  
can be met. t (max) is specified as a reference  
20. Output parameter (I/O) is referenced to corresponding  
CAS input, IO0~7 by CASL and IO8~15 by CASH .  
RAD  
RAD  
point only ; if t  
is greater than the specified t  
AA  
(max) limit, access time is controlled by t .  
21. Last falling CAS edge to first rising CAS edge.  
RCH  
RRH  
9. Either t  
or t  
must be satisfied for a READ cycle.  
22. Last rising CAS edge to next cycle’s last rising CAS  
edge.  
OFF1  
10.  
t
(max) defines the time at which the output  
achieves the open circuit condition ; it is not a  
23. Last rising CAS edge to first falling CAS edge.  
24. Each CAS must meet minimum pulse width.  
25. Referenced to the latter CAS falling edge.  
OH  
OL  
reference to V or V .  
WCS  
RWD  
AWD  
CWD  
11.  
t
, t  
, t  
and t  
are restrictive operating  
parameters in LATE WRITE and READ-MODIFY-  
WCS  
WCS(min)  
WRITE cycle only. If t  
t  
, the cycle is an  
26. All IOs controlled by OE , regardless CASL and  
CASH .  
EARLY WRITE cycle and the data output will remain  
RWD  
an open circuit throughout the entire cycle. If t  
27. Self refresh mode is initiated by performing a CBR  
refresh cycle and holding RAS low for the specified  
RASS  
RWD(min)  
AWD  
tAWD(min)  
CWD  
CWD(min)  
t  
, t  
and t  
t  
, the  
cycle is READ-WRITE and the data output will  
contain data read from the selected cell. If neither of  
the above conditions is met, the state of I/O (at  
access time and until CAS and RAS or OE go  
back to V ) is indeterminate. OE held high and  
taken low after CAS goes low result in a LATE  
WRITE ( OE -controlled) cycle.  
t
. Self refresh mode is terminated by rising RAS  
RPS  
high for a minimum time of t  
.
28. For all of the refresh mode expect the distributed CBR  
refresh mode, all rows must be refreshed within the  
refresh rate before and after self refresh.  
IH  
WE  
Elite Memory Technology Inc  
Publication Date: Agu. 2001  
Revision : 1.3  
6/16  
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