(OLWH07
Notes :
1.
2.
Enables on-chip refresh and address counters.
V
IH
(min) and V
IL
(max) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
.
In addition to meet the transition rate specification, all
input signals must transit between V
IH
and V
IL
in a
monotonic manner.
Assume that t
RCD
< t
RCD
(max). If t
RCD
is greater than
the maximum recommended value shown in this
table, t
RAC
will increase by the amount that t
RCD
exceeds the value shown.
Assume that t
RCD
≥
t
RCD
(max)
If
CAS
is low at the falling edge of
RAS
, data-out
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer,
CAS
and
RAS
must be pulsed high.
Operation within the t
RCD
limit ensures that t
RCD
(max)
can be met, t
RCD
(max) is specified as a reference
point only ; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled by t
CAC
.
Operation within the t
RAD
limit ensures that t
RAD
(max)
can be met. t
RAD
(max) is specified as a reference
point only ; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled by t
AA
.
Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
t
OFF1
(max) defines the time at which the output
achieves the open circuit condition ; it is not a
reference to V
OH
or V
OL
.
t
WCS
, t
RWD
, t
AWD
and t
CWD
are restrictive operating
parameters in LATE WRITE and READ-MODIFY-
WRITE cycle only. If t
WCS
≥
t
WCS(min)
, the cycle is an
EARLY WRITE cycle and the data output will remain
an open circuit throughout the entire cycle. If t
RWD
≥
t
RWD(min)
, t
AWD
≥
tAWD(min)
and t
CWD
≥
t
CWD(min)
, the
cycle is READ-WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the state of I/O (at
access time and until
CAS
and
RAS
or
OE
go
back to V
IH
) is indeterminate.
OE
held high and
WE
taken low after
CAS
goes low result in a LATE
WRITE (
OE
-controlled) cycle.
M11L416256A/M11L416256SA
12. Those parameters are referenced to
CAS
leading
edge in EARLY WRITE cycles and
WE
leading edge
in LATE WRITE or READ-MODIFY- WRITE cycles.
13. During a READ cycle, if
OE
is low then taken HIGH
before
CAS
goes high, I/O goes open, if
OE
is tied
permanently low, a LATE WRITE or READ-MODIFY-
WRITE operation is not possible.
14. An initial pause of 200
µ
s is required after power-up
followed by eight
RAS
refresh cycles (
RAS
only or
CBR) before proper device operation is assured. The
eight
RAS
cycle wake-ups should be repeated any
time the t
REF
refresh requirement is exceeded.
15. WRITE command is defined as
WE
going low.
16. LATE WRITE and READ-MODIFY-WRITE cycles must
have both tOFF2 and t
OEH
met (
OE
high during
WRITE cycle) in order to ensure that the output buffers
will be open during the WRITE cycles.
17. The I/Os open during READ cycles once t
OFF1
or t
OFF2
occur.
18. Referenced to the earlier
CAS
falling edge.
19. Referenced to the latter
CAS
rising edge.
20. Output parameter (I/O) is referenced to corresponding
CAS
input, IO0~7 by
CASL
and IO8~15 by
CASH
.
21. Last falling
CAS
edge to first rising
CAS
edge.
22. Last rising
CAS
edge to next cycle’s last rising
CAS
edge.
23. Last rising
CAS
edge to first falling
CAS
edge.
24. Each
CAS
must meet minimum pulse width.
25. Referenced to the latter
CAS
falling edge.
26. All IOs controlled by
OE
, regardless
CASL
and
CASH
.
27. Self refresh mode is initiated by performing a CBR
refresh cycle and holding
RAS
low for the specified
t
RASS
. Self refresh mode is terminated by rising
RAS
high for a minimum time of t
RPS
.
28. For all of the refresh mode expect the distributed CBR
refresh mode, all rows must be refreshed within the
refresh rate before and after self refresh.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Elite Memory Technology Inc
Publication Date: Agu. 2001
Revision
:
1.3
6/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
